@vmayoral thanks for keeping up with this regarding the ultra96. I believe that because of the many supported mezzanine boards available for this Zynq-based SOM and its relatively low cost, it is a great starting point for many who would participate in this group. I do have a few questions that, hopefully, can be addressed in the next WG meeting in a few weeks’ time. Here’s my first question:
- With regards to enabling devices connected via mezzanine or carrier board: How does the acceleration firmware concept apply to such cases?
What I am really asking is, based upon the whitepaper, I appreciate that the position you are taking for this working group is raising the level of abstraction for robotics developers to allow for greater flexibility and reducing the level of hardware expertise needed to make meaningful contributions, but it seems to me that some baseline proficiency with tools like Xilinx’s Vivado (or similar) is required to generate the hardware definition files for the target hardware. This leads to my second question:
- Where is the line drawn with regards to where this WG’s domain begins and the hardware concept design/implementation ends?
From my first reading of the white paper (which I gained much insight from, so thank you), it seems like a lot of emphasis was placed on acceleration kernels and optimization of interprocess, intraprocess, and intra-network communications. What, if any, emphasis will be placed on communication/connection to sensor devices and other peripherals?
I think I will pause my stream of thoughts here and I will revisit them based upon your reply to this thread. Thanks much for continuing support of this initiative, and I look forward to participating in this WG!