I can see the following in the Documentation topic areas which caught my interest and which seems reasonably high priority:
- Jetson Nano/ TX (Nvidia): All about better understanding Hardware acceleration
A. How Hardware accelerated ROS 2 pipelines for humble work? - ROS GEM packages
a. B. Usage demos on NVIDIA Isaac Transport
Hardware acceleration is a broad topic wherein there’re many things that can’t be achieved solely by Jetson Nano/TX. Also, this seems very NVIDIA-centric since AFAIK NVIDIA Isaac Transport is one of the implementations of REP 2007 and REP 2009. Will other implementations be documented as well? What’s the plan and rationale in here and who’s driving this?
Proper documentation about hardware acceleration shouldn’t focus on an specific technology/accelerator, but cover the topic broadly, introduce the concepts properly differentiating between accelerators, and then work with silicon vendors and the community to commit resources so that they contribute documentation for each of their specializations. We’ve been trying to do this in the HAWG for more than a year now.
In alignment with REP 2008 PR, the HAWG has been pushing contributions in a vendor-neutral manner, which helps ROS developers use the best resource for each use case (e.g. GPUs for vector-friendly computation applications, FPGAs for I/O interaction, etc) and jump across accelerators to avoid lock in (e.g. to cope with the semiconductor scarcity). Shouldn’t the same approach be adopted by TSC-driven initiatives?
I think the HAWG should be involved in this effort and steer this.
For what concerns hardware acceleration docs, I can help reviewing documentation proposals but overall, sticking to only one vendor of hardware acceleration will provide such vendor a huge (if you ask me, unfair) competitive edge which will turn into a negative effect for the community mid-term. Mainly because this will a) discourage other silicon vendors to continue investing (or start doing so) into ROS 2, and b) defeat the purpose we’ve been trying for a year at the HAWG encouraging other vendors to participate (note we have usually 4-5 vendors attending HAWG meetings and increasingly showing interest).
At the HAWG, we’ve produced demonstrators and walkthroughs in the form of ticket/issues which could be transformed into ROS documentation as a starting point, keeping a vendor-neutral general scope.
As for funding/time, similar to the meta-ros Humble port which was funded by HAWG members[1] and which was tested in various accelerators [2], I can try and reach out the various silicon vendors which might be interested on this and see who’s willing to commit resources to contribute to documentation and work with us at the HAWG.
Of course, this only makes since if the TSC defers to the Hardware Acceleration WG for hardware acceleration documentation.
Can someone please clarify this and provide answers to the questions raised above?
Reach out to AMD for resources to port Yocto recipes to Humble ROS 2 TSC Meeting January 20th, 2022 - #4 by vmayoral ↩︎
Humble support in Yocto (
Honister) and writeups for various accelerator solutions ROS 2 Humble Hawksbill Released! - #7 by vmayoral ↩︎