Sounds interesting! I’d be curious to learn more about which exact abstractions within ROS would be targeted. There’s a lot that can be done with FPGAs and it’s a great way to try out new dedicated hardware!
Glad to hear you also find it interesting @gbalke! FPGAs are indeed great for prototyping and accelerating specialized compute architectures in robotics. I highly encourage to read through [2009.06034] A Survey of FPGA-Based Robotic Computing which surveys nicely recent work on that direction.
To your question, initial plan as indicated in point 2. above is to focus on ROS 2 underlayers. Particularly and for starters, we’d like to empower ROS 2 users with capabilities to leverage time-sensitive communications at the Data Link layer (OSI L2) and obtain distributed sub-microsecond synchronization capabilities from the ROS 2 computational graph. This is strategic and core for distributed computational graphs as discussed in here. Without optimized computational graphs, it’ll be hard to leverage other accelerators since that’ll be the bottleneck.
ROS 2 stack Software stack OSI stack
+--------------------+ +--------------------+ +--------------------+
| user land | | | | |
+--------------------+ + + + +
| ROS client library |--->| | | |
+--------------------+ + ROS 2 + + 7. Application +
| middleware iface | | | | |
+--------------------+ + + + +
| DDS adapter | | | | |
+--------------------+ +--------------------+ | |
| | | | +--------------------+
| DDS impl |--->| DDS | | 6. Presentation |
| | | | +--------------------+
+--------------------+ | | | 5. Session |
+--------------------+ +--------------------+
| | | 4. Transport |
| UDP / IP | +--------------------+
| | | 3. Network |
+--------------------+ +--------------------+
| | | 2. Data Link |
| Ethernet | +--------------------+
| | | 1. Physical |
+--------------------+ +--------------------+
From there, HAWG should go up based on the input we get. We don’t have a specified order and that’s what this post is for, to get your input. We’ve heard in the past that it’d be awesome to run DDS in the Programmable Logic (PL, the FPGA itself) optimizing intra-network flows while leveraging specialized communication buses for nanosecond-level intra and inter-process communications. We also have some additional ideas ourselves but as pointed out, we’d love to hear your thoughts and needs.
One important aspect is that we don’t want HAWG to be just about FPGAs. It’d be a waste since many accelerators can nowadays be developed with OpenCL and modern C++ (leveraging HLS). We are hoping to create some “open” accelerators and inspire others to contribute impacting not just ROS 2, but also Gazebo. Wouldn’t it be awesome to supercharge our simulations with GPUs?