Future Robots are smarter and capable of making decisions in real-time. Decision making requires the use of AI for performing classification and semantic segmentation. Such AI algorithms require the use of dedicated hardware for making decisions at the edge. This group is meant for discussing subjects related to the integration of the:
The Xilinx Edge AI Platform provides comprehensive tools and models which utilize unique deep compression and hardware-accelerated Deep Learning technology.
The platform provides efficient, convenient and economical inference deployments for embedded-CPU-based FPGAs.
The Xilinx AI team consists of renowned researchers and experienced professionals known for their pioneering work in the field of deep learning.
… I am also totally biased, as I created Sundance’s VCS platform.
We wanted to use the EV version of the Zynq MPSoC to allow the “Edge-AI” to benefit from the integrated codecs, etc. + give more fabric and more memory. The VCS platform is also in Open Source, but has a much higher cost, intended for industrial application.
In my experience the xilinx workflow works really well, IF the model you are trying to deploy was built with the same version of caffe or tensorflow as your DECENT and DNNC. Trying to deploy pre-trained models you find online can be tricky and time-consuming (unless they come from the AI model zoo of course then you are one step removed from a DPU kernel). Deploying your own models should be fine if you align your environments.
I’m also interested to see if and when pytorch support arrives. I’m currently working with DNNDK on the ZCU102, maybe the newer VITIS AI (built on top of DNNDK) has support for more frameworks and easier integration of models built with/against different versions of tensorflow and caffe?
we did internally put some login in PL for doing pre-process for imaging (not so much i can share), and the CPU receives that pre-processed data and publishes as ROS topic. this is long time ago, but if i remember correctly, i did use ROS kinetic.
Hi @pedrombmachado, thank you for the invite, however we got a ZCU102 loaner to do some testing for a project. We will be handing that back over soon. So I am not sure if Ill be handling any FPGAs for the foreseeable future. I am interested in the subject in general, but I dont think I’ll be contributing much.
then you are one step removed from a DPU kernel). Deploying your own models should be fine if you align your environments.