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ROS2 Embedded SIG meeting #1



Following the current interest on a ROS 2 targeting microcontrollers we have scheduled an online community meeting for next Monday, 5th of November at 16:00-18:00 UTC.

The meeting will take place on hangouts meet:

The main point of this meeting would be to get some consensus on design and joint efforts on the development.

Currently, there is an in-progress PR with a draft of a design:

ROS2 Cross compilation

I was unable to make this meeting, are there any plans to post minutes?


Here you can find the meeting notes.
If any of the attendees want his names/companies removed from them I can do it.

ROS 2 Embedded SIG meeting Agenda 11/05

05 NOVEMBER 2018 17:00 PM, Hangouts Meet.


  • eProsima: Jaime Martin, Borja Outerelo
  • Bosch: Ingo Lütkebohle
  • Acutronic Robotics: Iñigo Muguruza
  • eSOL: Akihiko Tsukuda, Shoji Morita (supporting Renesas,
  • Amazon: Nick Burek
  • Renesas: Osamu “Max” Matshushima
  • AIST: Geoffrey Biggs


Quick presentations

Quick presentations on each of the attendees.
By turns, each of the attendees introduces themselves. Check Attendees section for the list.

Embedded ROS 2 Design

Summary of the current status of the design.
PR on ROS2 Design:

Original design doc from OFERA/microROS:


Ingo: What kind of devices we are targeting?

Geoffrey Biggs: Possible two targets:
Bigger devices using the current stack.
Smaller devices using something more like rosserial.

Iñigo: We are not very far from small devices on OFERA project we are squeezing the sizes with pretty good results (XRCE-DDS client is taking ~4k RAM)

Nick: We are looking at TurtleBot. We don’t think we need a smaller implementation.
They have one implementation targeting Arduino, extending TurtleBot that is already integrated on Arduino platform.

Ingo: May OSRF can help with some optimisations and modularisation on RCL and RMW.

Ingo & Geoffrey Biggs:
One of the most significant issues is the statically concept in RCL and RMW.

Ingo: We should engage OSRF for ensuring the success of this work. Some layers will need to be modified in future.

Current work review

List and review of currently available approaches.

Borja: The current release of OFERA/micro-ROS:

Project’s GitHub page:


Very thin wrapper over Micro XRCE-DDS with pretty simple basic ROS 2 concepts.
Don’t need to touch ROS 2 core.
Having a lot of rosserial users, It looks a good idea to have a migration path to ROS 2.

Open question: Is the use case people bringing ROS 2 nodes to microcontrollers or just implementing specific nodes?

Ingo: People worrying about minimal impact will do their custom implementation.
People on ROS 2 community side, may want the full stack approach.
If we can get RCL/RMW really small would be the ideal approach.

Nick: H-ROS is other interesting approach using microprocessors. But how small they are targeting?.

Iñigo: H-ROS uses H-RIM to set a standard information model to be able to plug and play components.
H-ROS would like to integrate microcontrollers.

Ingo: We plan to benchmark the memory usage of the provided solutions.
We think that the messages buffers are probably the biggest consumers.

Nick: Will be Lovely to have measures on current consumption of RMW and RCL

Osamu “Max” Matshushima: RTOS is the biggest consumer on the system. In our POC FreeRTOS uses more ram than Micro XRCE-DDS implementation. TCP/IP stack included.
Link to the source code?

Borja: You can select the protocol you want to use under micro XRCE-DDS: TCP, UDP, Serial even personalise yours.

Ingo: We use FreeRTOS on XDK, see

Further actions

Organisation and further actions of a joint effort towards embedded ROS 2.

Ingo: Trying to get further information on the RCL and RMW implementation.
Maybe engage in a discussion on the size of the layers once we have some data.

Iñigo & Ingo & Borja:
RTOS implementation for later.

Osamu “Max” Matshushima:
Provide POC code.


Provide some demos for memory usage measures.
Planning: Alternate time approach for setting meeting times.
Planning: Meets to be set for every two weeks.


Here is the memory usage of Renesas RX65N implementation. The memory size I discussed at the SIG meeting includes AWS and Mbed TLS which are the big memory consumers. If we don’t have to support the use-case, the memory usage becomes quite small (Use case 1 and 2). Please see the table below. Please note this memory usage could get changed during the course of development.

For RX65N FreeRTOS code, please see

Use case1: w/ UART

Flash RAM
FreeRTOS Kernel 10KB 0KB (allocated by heap/stack)
RX Driver Package 30KB 5KB
System heap/stack - 10KB
Total 90KB 20KB

Use case2: w/ Local Area Network

Flash RAM
Use case1 10KB 0KB (allocated by heap/stack)
RX Driver Package 30KB 5KB
FreeRTOS+TCP 20KB 0KB (allocated by heap/stack)
System heap/stack - 30KB
Total 110KB 40KB

Use case3: w/ full implementation: Wide Area Network

Flash RAM
FreeRTOS Kernel 10KB 0KB (allocated by heap/stack)
RX Driver Package 30KB 5KB
FreeRTOS+TCP 20KB 0KB (allocated by heap/stack)
Mbed TLS 110KB 20KB
System heap/stack - 130KB
Total 270KB 170KB


Please see for DDS-XRCE PoC code running on the Renesas RX65N MCU.