Happy new year all,
Hardware acceleration usage continue to grow across the ROS community and the robotics industry. The Hardware Acceleration Working Group (HAWG) continued growing significantly during 2023. Altogether, that is 3 years of continued work and growth (2021, 2022).
Key milestones of HAWG
Year | Objective |
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21 |
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21 |
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21 |
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22 |
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22 |
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22 |
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22 |
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22 |
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22 |
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22 |
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22 |
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22 |
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22 |
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23 |
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23 |
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23 |
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23 |
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23 |
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24 |
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24 |
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24 |
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Having accomplished most of the initial objectives of the working group when created back in 2021, and having supported multiple silicon vendors (Intel added last year) as part of the The ROS 2 Hardware Acceleration Stack, the working group will focus next on three objectives: the first objective is to continue working on demonstrators and case studies. We generated very exciting results within 2023 that we’ll expand during the next year and hopefully disclose publicly. The second objective will be to build upon the success[7] of the reference FPGA-based ROS 2 implementation for High-Speed Networking and explore other network accelerators. Some ideas include bridging between other communication middlewares or even pushing the speed of networking interactions faster. The third objective is to evolve the RobotPerf project, which attracted quite a few contributors already (see RobotPerf paper). Subgoals here would be to create more benchmark releases, add new benchmarking categories (with their corresponding benchmark implementations) and ultimately, expand the project to other communities which could benefit from it, all while remaining ROS-centric.
Happy to get feedback and/or coordinate contributions from others. Altogether, the objectives for the coming year so far look as follows:
Year | Objective |
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24 |
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24 |
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24 |
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Complete 2023 report available here.
See ament_vitis ↩︎
See acceleration_firmware_kv260 for an exemplary vendor extension of the
acceleration_firmware
package ↩︎Did not get buy-in from maintainers. Stopped the effort. ↩︎
Discarded for ROSCon and IROS. Lots of work. ↩︎
Reach out for more information about Intel’s enablement extensions of the ROS build system and build tools. ↩︎
After months of work, given preliminary results and expectations derived from those, we decided to pivot elsewhere and wrap the Robotics MCU project. Shortly, the performance obtained in RISC-V soft-core based ROS 2 implementations explored was not bringing much value on top of existing CPU implementations of ROS 2. Instead, we invested resources in exploring an FPGA-based ROS 2 implementation for High-Speed Networking. ↩︎
Our RTL implementation of the ROS 2 message-passing infrastructure can send or receive small ROS 2 messages in less than 2.5 us (one-way) and establish a round-trip communication within 5 us, accelerating average networking by more than 62x when compared to traditional software implementations on CPUs. When considering maximum latencies, our RTL implementation does Thousands-Fold (4540x) faster in these worst case scenarios than software ROS 2 implementations in modern CPUs. ↩︎